1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to demultiplexing of signals within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. Within certain communication systems, different types of coded signals are employed, and it is oftentimes desirable to transform a signal from a first coded signal type to a second coded signal type. One example of this transformation from a first coded signal type to a second coded signal type involves transforming a thermometer encoded signal to a binary coded signal.
The prior art means for performing this thermometer to binary transformation have a number of deficiencies including occupying a significant amount of real estate and also consuming a significant amount of power.
FIG. 6A and FIG. 6B illustrate prior art and ideal, non-realizable embodiments of combined demultiplexing and thermometer encoding.
Referring to the prior art embodiment 601 of FIG. 6A, this traditional architecture of a thermometer-to-binary DEMUX encoder (which can be referred to as a DEMUX encoder) de-multiplexes the thermometer encoded data firstly using a 1 to 4 DEMUX and then performs the thermometer-to-binary encoding thereon using an encoder.
One embodiment of such a prior art architecture uses a 1 to 4 DEMUX which contains 5 latches operating at frequency F, and 10 latches operating at F/2 with the number of bits being 63 through the entire DEMUX. The estimated power consumption, P, is calculated as follows:P=(Nbits)×(# of latches)×(frequency).P=63×5×F+63×10×(F/2)=630F. 
Referring to the ideal, yet non-realizable embodiment 602 of FIG. 6B, a best approach would be to place the encoder prior to the input of the DEMUX for a potential power savings as calculated as follows:P=(Nbits)×(# of latches)×(frequency).P=6×5×F+6×10×(F/2)=60F. 
This is a power savings of 90%, but this embodiment 602 is simply not always possible or realizable, especially for high speed applications.
There exists a need in the art for less power consumptive, yet realizable architectures for performing combined de-multiplexing and encoding while supporting increased/higher operational rates and data speeds.